On 11/3/2025 10:59 AM, Mitul Golani wrote:
Add function which resets all accumulated DC Balance parameters
whenever adaptive mode of VRR goes off. This helps to give a
fresh start when VRR is re-enabled.

Signed-off-by: Mitul Golani <[email protected]>
---
  drivers/gpu/drm/i915/display/intel_display.c |  1 +
  drivers/gpu/drm/i915/display/intel_vrr.c     | 13 +++++++++++++
  drivers/gpu/drm/i915/display/intel_vrr.h     |  2 ++
  3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 323293f4bf6d..b256517d58cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1149,6 +1149,7 @@ static void intel_pre_plane_update(struct 
intel_atomic_state *state,
        if (intel_crtc_vrr_disabling(state, crtc)) {
                intel_vrr_disable(old_crtc_state);
                intel_vrr_dcb_reset_flip_count(old_crtc_state, crtc);
+               intel_vrr_dcb_balance_reset(old_crtc_state, crtc);

Lets have both the reset functions in the intel_vrr_dcb_balance_reset().
Move this patch before the dcb_flip_count introduction patch.


Call the function to reset the flip_count from intel_vrr_dcb_balance_reset()


Regards,

Ankit


                intel_crtc_update_active_timings(old_crtc_state, false);
        }
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2ae27751e5b4..6168caff9cf0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -639,6 +639,19 @@ void intel_vrr_dcb_reset_flip_count(const struct 
intel_crtc_state *crtc_state,
        intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
  }
+void
+intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state,
+                           struct intel_crtc *crtc)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum pipe pipe = crtc->pipe;
+
+       if (!crtc_state->vrr.dc_balance.enable)
+               return;
+
+       intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
+}
+
  void intel_vrr_send_push(struct intel_dsb *dsb,
                         const struct intel_crtc_state *crtc_state)
  {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h 
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 8f97525b8e2d..a713d1a1e3dd 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -44,6 +44,8 @@ void intel_vrr_dcb_increment_flip_count(struct 
intel_crtc_state *crtc_state,
                                        struct intel_crtc *crtc);
  void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state,
                                    struct intel_crtc *crtc);
+void intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state,
+                                struct intel_crtc *crtc);
  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
  int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
  int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);

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