Since the clock rate is derived from the PLL divider values it can have
a +-1kHz difference wrt. the reference rates in the comparison

Signed-off-by: Mika Kahola <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 +++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c    | 18 ++++++++----------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0f28d02b7a69..ea807191cb4f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3013,6 +3013,12 @@ static void intel_c20_pll_program(struct intel_display 
*display,
                      MB_WRITE_COMMITTED);
 }
 
+static bool is_mplla_clock_rate(int clock)
+{
+       return intel_cx0pll_clock_matches(clock, 1000000) ||
+              intel_cx0pll_clock_matches(clock, 2000000);
+}
+
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
                                         const struct intel_cx0pll_state 
*pll_state,
                                         int port_clock,
@@ -3038,7 +3044,7 @@ static void intel_program_port_clock_ctl(struct 
intel_encoder *encoder,
 
        /* TODO: HDMI FRL */
        /* DP2.0 10G and 20G rates enable MPLLA*/
-       if (port_clock == 1000000 || port_clock == 2000000)
+       if (is_mplla_clock_rate(port_clock))
                val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
        else
                val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 055e68810d0d..63a88006e336 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -70,16 +70,14 @@
 
 bool intel_hdmi_is_frl(u32 clock)
 {
-       switch (clock) {
-       case 300000: /* 3 Gbps */
-       case 600000: /* 6 Gbps */
-       case 800000: /* 8 Gbps */
-       case 1000000: /* 10 Gbps */
-       case 1200000: /* 12 Gbps */
-               return true;
-       default:
-               return false;
-       }
+       u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(rates); i++)
+               if (intel_cx0pll_clock_matches(clock, rates[i]))
+                       return true;
+
+       return false;
 }
 
 static void
-- 
2.34.1

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