RE: [PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 MHz rate

[Kandpal, Suraj]

> Subject: [PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 MHz rate
> 
> Drop 27.2 MHz pll table as with these pll dividers the port clock will be
> incorrectly calculated to 27.0 MHz.
> For 27.2 MHz rate the PLl dividers are calculated algorithmically making pll
> table for this rate redundant.

*PLL
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kand...@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 55 ---------------------
>  1 file changed, 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 13acfc7c0469..bc73b1466bc4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -801,60 +801,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_252 = {
>       },
>  };
> 
> -static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
> -     .clock = 27200,
> -     .config = {
> -             0x84,
> -             0x2d,
> -             0x0,
> -     },
> -     .addr_msb = {
> -             0x87,
> -             0x87,
> -             0x87,
> -             0x87,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -             0x88,
> -     },
> -     .addr_lsb = {
> -             0x10,
> -             0x0c,
> -             0x14,
> -             0xe4,
> -             0x0c,
> -             0x10,
> -             0x14,
> -             0x18,
> -             0x48,
> -             0x40,
> -             0x4c,
> -             0x24,
> -             0x44,
> -     },
> -     .data = {
> -             { 0x0,  0x4c, 0x2,  0x0  },
> -             { 0x0b, 0x15, 0x26, 0xa0 },
> -             { 0x60, 0x0,  0x0,  0x0  },
> -             { 0x8,  0x4,  0x96, 0x28 },
> -             { 0xfa, 0x0c, 0x84, 0x11 },
> -             { 0x80, 0x0f, 0xd9, 0x53 },
> -             { 0x86, 0x0,  0x0,  0x0  },
> -             { 0x1,  0xa0, 0x1,  0x0  },
> -             { 0x4b, 0x0,  0x0,  0x0  },
> -             { 0x28, 0x0,  0x0,  0x0  },
> -             { 0x0,  0x14, 0x2a, 0x14 },
> -             { 0x0,  0x0,  0x0,  0x0  },
> -             { 0x0,  0x0,  0x0,  0x0  },
> -     },
> -};
> -
>  static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
>       .clock = 74250,
>       .config = {
> @@ -1019,7 +965,6 @@ static const struct intel_lt_phy_pll_state
> xe3plpd_lt_hdmi_5p94 = {
> 
>  static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
>       LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
> -     LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
>       LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
>       LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
>       LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
> --
> 2.34.1