> Subject: [PATCH v2 01/15] drm/i915/c10: Move C10 port clock calculation > > Prepare removal of .clock member from pll state structures by moving > intel_c10pll_calc_port_clock() function. > > No functional changes. > > Signed-off-by: Mika Kahola <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 54 ++++++++++---------- > 1 file changed, 27 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f6d69627154e..5fb39c114078 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2103,6 +2103,33 @@ static bool cx0pll_state_is_dp(const struct > intel_cx0pll_state *pll_state) > return c20pll_state_is_dp(&pll_state->c20); > } > > +static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, > + const struct intel_c10pll_state > *pll_state) { > + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; > + unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; > + int tmpclk = 0; > + > + if (pll_state->pll[0] & C10_PLL0_FRACEN) { > + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; > + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; > + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; > + } > + > + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, > pll_state->pll[3]) << 8 | > + pll_state->pll[2]) / 2 + 16; > + > + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, > pll_state->pll[15]); > + hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state- > >pll[15]); > + > + tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier > << 16) + frac_quot) + > + DIV_ROUND_CLOSEST(refclk * frac_rem, > frac_den), > + 10 << (tx_clk_div + 16)); > + tmpclk *= (hdmi_div ? 2 : 1); > + > + return tmpclk; > +} > + > /* > * TODO: Convert the following to align with intel_c20pll_find_table() and > * intel_c20pll_calc_state_from_table(). > @@ -2166,33 +2193,6 @@ static int intel_c10pll_calc_state(const struct > intel_crtc_state *crtc_state, > return 0; > } > > -static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, > - const struct intel_c10pll_state > *pll_state) > -{ > - unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; > - unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; > - int tmpclk = 0; > - > - if (pll_state->pll[0] & C10_PLL0_FRACEN) { > - frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; > - frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; > - frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; > - } > - > - multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, > pll_state->pll[3]) << 8 | > - pll_state->pll[2]) / 2 + 16; > - > - tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, > pll_state->pll[15]); > - hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state- > >pll[15]); > - > - tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier > << 16) + frac_quot) + > - DIV_ROUND_CLOSEST(refclk * frac_rem, > frac_den), > - 10 << (tx_clk_div + 16)); > - tmpclk *= (hdmi_div ? 2 : 1); > - > - return tmpclk; > -} > - > static int readout_enabled_lane_count(struct intel_encoder *encoder) { > struct intel_display *display = to_intel_display(encoder); > -- > 2.34.1
