> Subject: [PATCH v2 22/24] drm/i915/lt_phy: Add xe3plpd Thunderbolt pll > hooks
* PLL > > Add the PLL hooks for the TBT PLL on xe3plpd. These are simple stubs similarly * similar to the ... > to the TBT PLL on earlier platforms, since this PLL is always on from the > display > POV - so no PLL enable/disable programming is required as opposed to the > non-TBT PLLs - and the clocks for different link rates are enabled/disabled > at a > different level, via the > intel_encoder::enable_clock()/disable_clock() interface. > With above fixed LGTM Reviewed-by: Suraj Kandpal <[email protected]> > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++-- > drivers/gpu/drm/i915/display/intel_lt_phy.c | 18 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_lt_phy.h | 4 ++++ > 3 files changed, 33 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 28c560417409..534cc691979f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -4618,6 +4618,13 @@ static void xe3plpd_pll_disable(struct intel_display > *display, > intel_xe3plpd_pll_disable(encoder); > } > > +static const struct intel_dpll_funcs xe3plpd_tbt_pll_funcs = { > + .enable = mtl_tbt_pll_enable, > + .disable = mtl_tbt_pll_disable, > + .get_hw_state = intel_lt_phy_tbt_pll_readout_hw_state, > + .get_freq = mtl_tbt_pll_get_freq, > +}; > + > static const struct intel_dpll_funcs xe3plpd_pll_funcs = { > .enable = xe3plpd_pll_enable, > .disable = xe3plpd_pll_disable, > @@ -4628,7 +4635,8 @@ static const struct intel_dpll_funcs > xe3plpd_pll_funcs = { static const struct dpll_info xe3plpd_plls[] = { > { .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id = > DPLL_ID_ICL_DPLL0, }, > { .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id = > DPLL_ID_ICL_DPLL1, }, > - /* TODO: Add TBT */ > + { .name = "TBT PLL", .funcs = &xe3plpd_tbt_pll_funcs, .id = > DPLL_ID_ICL_TBTPLL, > + .is_alt_port_dpll = true, .always_on = true }, > { .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id = > DPLL_ID_ICL_MGPLL1, }, > { .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id = > DPLL_ID_ICL_MGPLL2, }, > { .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id = > DPLL_ID_ICL_MGPLL3, }, @@ -4671,7 +4679,8 @@ static int > xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state, > struct icl_port_dpll *port_dpll; > int ret; > > - /* TODO: Add state calculation for TBT PLL */ > + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; > + intel_lt_phy_tbt_pll_calc_state(&port_dpll->hw_state); > > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; > ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll- > >hw_state); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index 232f14d69ec8..746b0182362a 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -1766,6 +1766,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state > *crtc_state, > return -EINVAL; > } > > +void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state > +*hw_state) { > + memset(hw_state, 0, sizeof(*hw_state)); > + > + hw_state->ltpll.tbt_mode = true; > +} > + > static void > intel_lt_phy_program_pll(struct intel_encoder *encoder, > const struct intel_lt_phy_pll_state *ltpll) @@ -2208,6 > +2215,17 @@ static bool intel_lt_phy_pll_is_enabled(struct intel_encoder > *encoder) > intel_lt_phy_get_pclk_pll_ack(lane); > } > > +bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display, > + struct intel_dpll *pll, > + struct intel_dpll_hw_state > *hw_state) { > + memset(hw_state, 0, sizeof(*hw_state)); > + > + hw_state->ltpll.tbt_mode = true; > + > + return true; > +} > + > bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, > struct intel_lt_phy_pll_state > *pll_state) { > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h > b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index 3838e9326773..1c2ec438cd10 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -26,6 +26,7 @@ int > intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder, > struct intel_dpll_hw_state *hw_state); > +void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state > +*hw_state); > int intel_lt_phy_calc_port_clock(struct intel_display *display, > const struct intel_lt_phy_pll_state *lt_state); > void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, @@ -35,6 > +36,9 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p, bool > intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, > const struct intel_lt_phy_pll_state *b); > +bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display, > + struct intel_dpll *pll, > + struct intel_dpll_hw_state > *hw_state); > bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, > struct intel_lt_phy_pll_state > *pll_state); > void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state, > -- > 2.43.0
