In xe3+, soc can lower the fabric frequency when the display
needs less bandwidth than the minimum GV point.
v1: pmdemand peak bw is updated to 20GB/s is the required data rate
is low and less than 20GB/s even though there are no QGV point
with 20GB/s. Only the peak_ww is changed based on the conditions
v2: At the time of BW info calculations, a new row is inserted with
peakbw as 20GB/s and deratebw also to 20GB/s and the required
pmdemand peakbw is automatically calculated based on the old
logic.
Vinod Govindapillai (11):
drm/i915/wm: clear the plane ddb_y entries on plane disable
drm/i915/pm_demand: introduce HAS_PMDEMAND macro
drm/i915/display: sagv pre/post plane calls to check pmdemand support
drm/i915/bw: Extract icl_init_qgv_info()
drm/i915/bw: sort the qgv points based on the dclk
drm/i915/bw: update the routine to get max dclk from qgv points
drm/i915/bw: update the routine to find the peakbw in MTL
drm/i915/bw: update the tile-y dependency based on the display version
drm/i915/bw: consolidate the debug info of bw/dgv/psf data
drm/i915/bw: extract update_sagv_status()
drm/i915/bw: insert a sw bw info entry to cater low data rate usecases
drivers/gpu/drm/i915/display/intel_bw.c | 215 +++++++++++++-----
.../drm/i915/display/intel_display_device.h | 2 +
.../gpu/drm/i915/display/intel_display_irq.c | 2 +-
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 12 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
6 files changed, 178 insertions(+), 65 deletions(-)
--
2.43.0
