Consolidate the tile-y dependency into a separate function and use it to determine whether tile-y need to take into account for the bw calculations. Especially for post MTL cases, as per the bspec, no need to take the tile_y into account for the de interleave values.
Bspec: 64631, 68859 Signed-off-by: Vinod Govindapillai <[email protected]> --- drivers/gpu/drm/i915/display/intel_bw.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 177c3fd8f74a..858da1710a61 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -483,12 +483,21 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = { .derating = 10, }; +static bool is_tile_y_factored(struct intel_display *display) +{ + /* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */ + if (DISPLAY_VER(display) >= 14) + return false; + + return true; +} + static int icl_get_bw_info(struct intel_display *display, const struct dram_info *dram_info, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; - bool is_y_tile = true; /* assume y tile may be used */ + bool is_y_tile = is_tile_y_factored(display); int num_channels = max_t(u8, 1, dram_info->num_channels); int ipqdepth, ipqdepthpch = 16; int dclk_max; @@ -559,7 +568,7 @@ static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; - bool is_y_tile = true; /* assume y tile may be used */ + bool is_y_tile = is_tile_y_factored(display); int num_channels = max_t(u8, 1, dram_info->num_channels); int ipqdepth, ipqdepthpch = 16; int dclk_max; -- 2.43.0
