> Subject: [PATCH 2/2] drm/i915/psr: Allow SCL=0 on platforms with always-on > VRR TG > > For Legacy timing generator, if there are no panel replay/sel_update or other > SRD constraints, the Set context latency (SCL) window should be at least 1. > > However, for VRR timing generator the SCL window can be 0. It has other > guardband constraints, but that are checked during guardband computation. > > Allow SCL to be 0 for platforms that have VRR TG always on.
Maybe something around the lines of "Allow minimum SCL be 0 ...." Otherwise LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index f6cd88902be9..f0350e7f76a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1488,6 +1488,9 @@ int _intel_psr_min_set_context_latency(const struct > intel_crtc_state *crtc_state > needs_panel_replay) > return 0; > > + if (intel_vrr_always_use_vrr_tg(display)) > + return 0; > + > return 1; > } > > -- > 2.45.2
