On Mon, May 18, 2026 at 09:24:51AM +0530, Ankit Nautiyal wrote:
> Introduce a helper to check if Panel Replay has Async Video Timing support
> during PR Active state.
> 
> v2: Confirm that Panel Replay is supported before checking for
>     Async Video Timing Support during PR active. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <[email protected]>

Reviewed-by: Ville Syrjälä <[email protected]>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h |  1 +
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 892d209dce1b..431468103f51 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4655,3 +4655,14 @@ bool intel_psr_use_trans_push(const struct 
> intel_crtc_state *crtc_state)
>  
>       return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
>  }
> +
> +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp)
> +{
> +     struct intel_connector *connector = intel_dp->attached_connector;
> +     u8 *dpcd = connector->dp.panel_replay_caps.dpcd;
> +     u8 pr_support = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)];
> +     u8 pr_cap = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
> +
> +     return (pr_support & DP_PANEL_REPLAY_SUPPORT) &&
> +             !(pr_cap & 
> DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h 
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 394b641840b3..29723e63888f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp 
> *intel_dp,
>                                  struct intel_crtc_state *crtc_state);
>  int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>  bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
> +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp);
>  
>  #endif /* __INTEL_PSR_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

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