On Mon, May 18, 2026 at 09:24:57AM +0530, Ankit Nautiyal wrote: > If a Panel Replay capable sink, supports Async Video timing in > PR active state, then source does not necessarily need to send AS SDPs > during PR active. > > However, if asynchronous video timing is not supported, then for PR with > Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video > timing synchronization while PR is active. > > If the source needs to send AS SDP during PR active, this requires setting > DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether > VRR is enabled (AVT/FAVT) or fixed-timing mode is used. > > This bit defines AS SDP timing behavior during PR Active, even if AS SDPs > are briefly suspended. > > Program the relevant Downspread Ctrl DPCD bits accordingly. > > v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville) > v3: Since the bit is defined in context of Panel Replay and AS SDP, add > a check for both. (Ville) > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > .../gpu/drm/i915/display/intel_dp_link_training.c | 15 +++++++++++++-- > .../gpu/drm/i915/display/intel_dp_link_training.h | 3 ++- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > 3 files changed, 16 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index a26094223f78..d0b033d2cfb4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -34,8 +34,10 @@ > #include "intel_dp.h" > #include "intel_dp_link_training.h" > #include "intel_encoder.h" > +#include "intel_hdmi.h" > #include "intel_hotplug.h" > #include "intel_panel.h" > +#include "intel_psr.h" > > #define LT_MSG_PREFIX > "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " > #define LT_MSG_ARGS(_intel_dp, _dp_phy) > (_intel_dp)->attached_connector->base.base.id, \ > @@ -710,11 +712,14 @@ static bool intel_dp_link_max_vswing_reached(struct > intel_dp *intel_dp, > return true; > } > > -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int > link_rate, bool is_vrr) > +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int > link_rate, > + bool is_vrr, > + bool pr_with_as_sdp_enable) > { > u8 link_config[2]; > > link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; > + link_config[0] |= pr_with_as_sdp_enable ? > DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0; > link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? > DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; > drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); > @@ -723,6 +728,10 @@ void intel_dp_link_training_set_mode(struct intel_dp > *intel_dp, int link_rate, b > static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, > const struct intel_crtc_state > *crtc_state) > { > + bool pr_with_as_sdp_enable = > + intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) && > + crtc_state->infoframes.enable & > intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
This whole thing could be a function instead of a variable. The use of intel_psr_needs_alpm_aux_less() is a bit confusing here, but I guess it (at least currently) does the right thing. Reviewed-by: Ville Syrjälä <[email protected]> > + > /* > * Currently, we set the MSA ignore bit based on vrr.in_range. > * We can't really read that out during driver load since we don't have > @@ -737,7 +746,9 @@ static void intel_dp_update_downspread_ctrl(struct > intel_dp *intel_dp, > * especially on the first real commit when clearing the inherited > flag. > */ > intel_dp_link_training_set_mode(intel_dp, > - crtc_state->port_clock, > crtc_state->vrr.in_range); > + crtc_state->port_clock, > + crtc_state->vrr.in_range, > + pr_with_as_sdp_enable); > } > > void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h > index 33dcbde6a408..18c34c1a472f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h > @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp > *intel_dp); > bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp); > > void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, > - int link_rate, bool is_vrr); > + int link_rate, bool is_vrr, > + bool pr_with_as_sdp_enable); > void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, > int link_bw, int rate_select, int lane_count, > bool enhanced_framing, bool post_lt_adj_req); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 8f73e01db17c..a238f7948cec 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -2145,7 +2145,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp > *intel_dp) > > intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select); > > - intel_dp_link_training_set_mode(intel_dp, link_rate, false); > + intel_dp_link_training_set_mode(intel_dp, link_rate, false, false); > intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, > lane_count, > > drm_dp_enhanced_frame_cap(intel_dp->dpcd), false); > > -- > 2.45.2 -- Ville Syrjälä Intel
