On Mon, May 18, 2026 at 09:24:52AM +0530, Ankit Nautiyal wrote: > eDP v1.5a advertises support for Adaptive Sync SDP and with that the > support for AS SDP v2 is mandatory. > > DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD > 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2 > (AS SDP v2), which allows the source to set the version in HB2[4:0] and the > payload length in HB3[5:0] of the AS SDP header. > > DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the > Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink > does not support asynchronous video timing while in a Panel Replay Active > state and the source is required to keep transmitting Adaptive-Sync > SDPs. The spec mandates that such sinks shall support AS SDP v2. > > Infer AS SDP v2 support from these capabilities and store it in > struct intel_dp for use by subsequent feature enablement changes. > > v2: > - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to > determine AS SDP v2 support. (Ville) > v3: > - Use helper to determine asynch video timing support. > v4: > - Add AS SDP v2 support for eDP as per v1.5a. > - Add a check for Panel Replay support before checking for Async video > timing support in PR > - Add a TODO for Display ID and PCON considerations. (Ville) > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 49 +++++++++++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index b7bcf8fefa3e..e9b95879c797 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1871,6 +1871,7 @@ struct intel_dp { > /* connector directly attached - won't be use for modeset in mst world > */ > struct intel_connector *attached_connector; > bool as_sdp_supported; > + bool as_sdp_v2_supported; > > struct drm_dp_tunnel *tunnel; > bool tunnel_suspended:1; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 1920d2f02666..92a650a728d8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6365,6 +6365,46 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > false); > } > > +static bool > +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp) > +{ > + u8 rx_features; > + > + /* > + * The DP spec does not explicitly provide the AS SDP v2 capability. > + * So based on the DP v2.1 SCR, we infer it from the following bits: > + * > + * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for > + * FAVT, which is explicitly defined to use AS SDP v2. > + * > + * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink > + * does not support asynchronous video timing while in PR Active, > + * requiring the source to keep transmitting Adaptive-Sync SDPs. The > + * spec mandates that such sinks shall support AS SDP v2. > + * > + * #TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID > + * parsing is available. This may help detect AS SDP v2 support for > + * native DP 2.1 sinks that do not expose FAVT or PR-based capability > + * bits. > + * > + * In the presence of PCONs, check PCON support from DPCD and sink > + * support from Display ID. > + */ > + > + if (drm_dp_dpcd_read_byte(&intel_dp->aux, > + DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, > + &rx_features) == 1) { > + if (rx_features & > DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED) > + return true; > + } > + > + if (intel_dp->psr.sink_panel_replay_support && > + !intel_psr_pr_async_video_timing_supported(intel_dp)) > + return true; > + > + return false; > +} > + > static void > intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) > { > @@ -6372,6 +6412,15 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) > > intel_dp->as_sdp_supported = HAS_AS_SDP(display) && > drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); > + > + if (!intel_dp->as_sdp_supported) > + return; > + > + /* eDP Adaptive-Sync SDP always uses AS SDP v2 */ > + if (intel_dp_is_edp(intel_dp)) > + intel_dp->as_sdp_v2_supported = true;
I really hope eDP 1.5 (not 1.5a) was never adopted by anyone because it seems to make a complete mess of the AS SDP version number. Reviewed-by: Ville Syrjälä <[email protected]> > + else > + intel_dp->as_sdp_v2_supported = > intel_dp_sink_supports_as_sdp_v2(intel_dp); > } > > static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool > force_on_external) > -- > 2.45.2 -- Ville Syrjälä Intel
