DP spec says uisng FEC is mandatory if Panel Replay is enabled. Enable FEC for DP Panel Replay.
Signed-off-by: Jouni Högander <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2f36d34ab6871..52af6319691c1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2494,7 +2494,8 @@ bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return false; - return dsc_enabled_on_crtc || intel_fec_enabled_on_link(crtc_state); + return dsc_enabled_on_crtc || intel_fec_enabled_on_link(crtc_state) || + crtc_state->has_panel_replay; } void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state) @@ -3678,6 +3679,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_psr_pre_compute_config(intel_dp, pipe_config, conn_state); + pipe_config->fec_enable = intel_dp_needs_8b10b_fec(pipe_config, false); + /* * Try to respect downstream TMDS clock limits first, if * that fails assume the user might know something we don't. diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a2675defaa3bf..28d3b4aca9b10 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -642,6 +642,8 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode intel_psr_pre_compute_config(intel_dp, pipe_config, conn_state); + pipe_config->fec_enable = intel_dp_needs_8b10b_fec(pipe_config, true); + /* enable compression if the mode doesn't fit available BW */ if (dsc_needed) { int dsc_slice_count; -- 2.43.0
