On 6/8/2026 7:41 PM, Jouni Högander wrote:
Intel_dsc_enabled_on_link is not really about DSC being enabled on crtc. It
is telling if FEC is enabled on link.
Hmm... This is a bit unclear to me.
As per commit 470b84af457e ("drm/i915/dp_mst: Recompute all MST link
CRTCs if DSC gets enabled on the link")
We wanted to do away with FEC tracking, and instead tracked DSC. FEC for
UHBR was not getting filled so it makes sense to track DSC (FEC being
mandatory for DP DSC).
From commit message for commit 470b84af457e
"...
Based on the above, to be able to determine the DSC state on both
non-UHBR and UHBR MST links, track the more generic DSC-enabled-on-link
state (instead of the FEC-enabled-on-link state) for each CRTC in
intel_link_bw_limits."
So to me it appears that we were actually concerned about DSC and not
FEC and started using intel_dsc_enabled_on_link()
(later, fec_enable was unused and removed).
Perhaps I am missing some context?
Instead of intel_dsc_enabled_on_link
check status directly from crtc->dsc.compression_enable.
I agree to this part though. We can separate it out in any case.
Regards,
Ankit
Also rename intel_dsc_enabled_on_link as intel_fec_enabled_on_link.
Signed-off-by: Jouni Högander <[email protected]>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index ad2f6c79f5808..f58200d38ac2c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1740,7 +1740,7 @@ static bool intel_sel_update_config_valid(struct
intel_crtc_state *crtc_state,
if (!connector->dp.panel_replay_caps.su_support)
goto unsupported;
- if (intel_dsc_enabled_on_link(crtc_state) &&
+ if (crtc_state->dsc.compression_enable &&
connector->dp.panel_replay_caps.dsc_support !=
INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
drm_dbg_kms(display->drm,
@@ -1840,7 +1840,7 @@ static bool _panel_replay_compute_config(struct
intel_crtc_state *crtc_state,
return false;
}
- if (intel_dsc_enabled_on_link(crtc_state) &&
+ if (crtc_state->dsc.compression_enable &&
connector->dp.panel_replay_caps.dsc_support ==
INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
drm_dbg_kms(display->drm,
@@ -3235,7 +3235,7 @@ verify_panel_replay_dsc_state(const struct
intel_crtc_state *crtc_state)
return;
drm_WARN_ON(display->drm,
- intel_dsc_enabled_on_link(crtc_state) &&
+ crtc_state->dsc.compression_enable &&
crtc_state->panel_replay_dsc_support ==
INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8f06c3a4d56df..35c93fcbb6427 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -431,7 +431,7 @@ void intel_dsc_enable_on_crtc(struct intel_crtc_state
*crtc_state)
crtc_state->dsc.compression_enable = true;
}
-bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state)
+bool intel_fec_enabled_on_link(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 3372f8694054d..60d86399808c0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -28,7 +28,7 @@ void intel_dsc_enable(const struct intel_crtc_state
*crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
-bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state);
+bool intel_fec_enabled_on_link(const struct intel_crtc_state *crtc_state);
void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
cpu_transcoder);
