The LFPS Half Cycle Duration field, as well as the First and Last LFPS Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per Bspec the value programmed must be N_Symbol - 1. get_lfps_half_cycle_clocks() returned N_Symbol and programmed it directly into all three fields, making each half cycle one symbol clock too long.
Return N_Symbol - 1 so the programmed value matches the zero-based field encoding. Bspec: 71632 Cc: Jouni Högander <[email protected]> Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 5d2ac7561567..9768279f94ef 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -123,8 +123,16 @@ static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state) static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state) { - return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 / - 1000 / (2 * get_lfps_cycle_count(crtc_state)); + int n_symbols = get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / + 1000 / 1000 / (2 * get_lfps_cycle_count(crtc_state)); + + /* + * The LFPS half cycle duration fields (including the first and last + * half cycle) are zero-based, i.e. the value programmed is N_Symbol - 1. + * + * Bspec: 71632 + */ + return n_symbols - 1; } #define ML_PHY_LOCK_LEN 252 -- 2.29.0
