> -----Original Message-----
> From: Hogander, Jouni <[email protected]>
> Sent: Wednesday, September 2, 2026 3:07 PM
> To: [email protected]; Manna, Animesh
> <[email protected]>; [email protected]
> Cc: Kandpal, Suraj <[email protected]>; Nikula, Jani
> <[email protected]>
> Subject: Re: [PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS
> for LT PHY
>
> On Tue, 2026-08-25 at 11:15 +0530, Animesh Manna wrote:
> > Enable MAC to transmit LFPS via LT PHY during aux-less alpm.
> >
> > v2:
> > - Correct commit description. [Suraj]
> > - Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0.
> > [Suraj]
> > v3: Cosmetic changes. [Suraj]
> >
> > Cc: Jouni Högander <[email protected]>
> > Reviewed-by: Suraj Kandpal <[email protected]>
> > Signed-off-by: Animesh Manna <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 27
> > +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 ++
> > .../gpu/drm/i915/display/intel_lt_phy_regs.h | 3 +++
> > 4 files changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 9b3b526e5e55..5244218132aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3796,7 +3796,10 @@ static void
> > mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0"
> > PIPE
> > * register
> > */
>
> I think you need to update comment above. Otherwise patch looks ok.
Both case am writing to respective "PHY Common Control 0".
Regards,
Animesh
>
> BR,
> Jouni Högander
>
> > - intel_lnl_mac_transmit_lfps(encoder, crtc_state);
> > + if (HAS_LT_PHY(display))
> > + intel_xe3plpd_mac_transmit_lfps(encoder,
> > crtc_state);
> > + else
> > + intel_lnl_mac_transmit_lfps(encoder, crtc_state);
> > }
> >
> > static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 86492651b01d..4fe010df20be 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -5,6 +5,7 @@
> >
> > #include <drm/drm_print.h>
> >
> > +#include "intel_alpm.h"
> > #include "intel_cx0_phy.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > @@ -2357,3 +2358,29 @@ void intel_lt_phy_verify_plls(struct
> > intel_display *display)
> > intel_lt_phy_pll_verify_tables(display,
> > xe3plpd_lt_edp_tables);
> > intel_lt_phy_pll_verify_tables(display,
> > xe3plpd_lt_hdmi_tables);
> > }
> > +
> > +/*
> > + * According to HAS we need to enable MAC Transmitting LFPS in the
> > "PHY Common
> > + * Control 0" PIPE register in case of AUX Less ALPM is going to be
> > used. This
> > + * function is doing that and is called by link retrain sequence.
> > + */
> > +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + struct ref_tracker *wakeref;
> > + u8 owned_lane_mask;
> > +
> > + if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> > + return;
> > +
> > + wakeref = intel_lt_phy_transaction_begin(encoder);
> > +
> > + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> > +
> > + intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0,
> > + LT_PHY_CMN_LFPS_ENABLE,
> > + LT_PHY_CMN_LFPS_ENABLE,
> > MB_WRITE_COMMITTED);
> > +
> > + intel_lt_phy_transaction_end(encoder, wakeref); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > index 16de39484779..c76c97b90946 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > @@ -49,5 +49,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder
> > *encoder,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> > void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> > void intel_lt_phy_verify_plls(struct intel_display *display);
> > +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state);
> >
> > #endif /* __INTEL_LT_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index ff6d7829dbb9..b64ff57e0c09 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -35,6 +35,9 @@
> > #define LT_PHY_TXY_CTL10_MAC(idx)
> _MMIO(LT_PHY_TXY_CTL10(idx))
> > #define LT_PHY_TX_LANE_ENABLE REG_BIT8(0)
> >
> > +#define LT_PHY_CMN_CTL_0 (0x800)
> > +#define LT_PHY_CMN_LFPS_ENABLE REG_BIT8(1)
> > +
> > /* LT Phy Vendor Register */
> > #define LT_PHY_VDR_0_CONFIG 0xC02
> > #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)
