Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Incorrect register bit mask selection for LFPS cycle count based on connector type instead of hardware IP version. --
--- Patch [9]: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM --- commit f40607bd1107960e9e7fba56539c2f142247127f Author: Animesh Manna <[email protected]> drm/i915/alpm: Modify LFPS cycle count for DP ALPM This commit modifies the display driver to set a minimum LFPS cycle count of 16 for external DP on newer display IPs. > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c > b/drivers/gpu/drm/i915/display/intel_alpm.c > index 98aa418a6ff77..890bf24885547 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c [ ... ] > @@ -622,12 +635,21 @@ void intel_alpm_port_configure(struct intel_dp > *intel_dp, > return; > > if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { > + int lfps_cycle = get_lfps_cycle_count(crtc_state); > + u32 lfps_cycle_val; > + > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + lfps_cycle_val = > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle); > + else > + lfps_cycle_val = > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle); ^^^^ [Severity: Medium] Does this code incorrectly conflate the sink type with the display IP version? In intel_alpm_port_configure(), branching on the connector type (INTEL_OUTPUT_EDP) rather than the hardware IP version causes eDP panels on Xe3LPD to be programmed using the legacy 4-bit register mask instead of the expanded 7-bit Xe3LPD mask. While the current default value for eDP (10 cycles) happens to fit within the lower 4 bits, if the eDP LFPS cycle count is ever tuned to a value > 22, the legacy 4-bit mask will truncate it and could corrupt the hardware configuration. Should this logic check the display version instead of the output type? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=9
