From: Ankit Nautiyal <[email protected]>
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.
Add support for these extra bits.
For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.
v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
v5: Drop a stale changelog entry, the DISPLAY_VER split here is
intentional. (Sashiko)
Bspec: 50488
Signed-off-by: Ankit Nautiyal <[email protected]>
Co-developed-by: Suraj Kandpal <[email protected]>
Signed-off-by: Suraj Kandpal <[email protected]>
Reviewed-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++--
.../gpu/drm/i915/display/intel_display_regs.h | 2 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f74e7ddf0e41..461b81bf8341 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,14 +2720,22 @@ void intel_set_m_n(struct intel_display *display,
intel_reg_t data_m_reg, intel_reg_t data_n_reg,
intel_reg_t link_m_reg, intel_reg_t link_n_reg)
{
+ u32 link_n = m_n->link_n;
+
intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
intel_de_write(display, data_n_reg, m_n->data_n);
intel_de_write(display, link_m_reg, m_n->link_m);
+
+ if (DISPLAY_VER(display) >= 14)
+ link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+ else
+ link_n &= DATA_LINK_M_N_MASK;
+
/*
* On BDW+ writing LINK_N arms the double buffered update
* of all the M/N registers, so it must be written last.
*/
- intel_de_write(display, link_n_reg, m_n->link_n);
+ intel_de_write(display, link_n_reg, link_n);
}
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3484,7 +3492,13 @@ void intel_get_m_n(struct intel_display *display,
intel_reg_t link_m_reg, intel_reg_t link_n_reg)
{
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
- m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+ m_n->link_n = intel_de_read(display, link_n_reg);
+
+ if (DISPLAY_VER(display) >= 14)
+ m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+ else
+ m_n->link_n &= DATA_LINK_M_N_MASK;
+
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display,
data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2f509bd06557..983a0d9dcb9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
#define _PIPEA_LINK_N1 0x60044
#define _PIPEB_LINK_N1 0x61044
+#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24)
+#define PIPE_LINK_N1_EXTENDED(val)
REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
_PIPEA_LINK_N1)
#define _PIPEA_LINK_M2 0x60048
--
2.34.1
