For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.
This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266
Ankit Nautiyal (8):
drm/i915/display: Add helper to compute link M/N ratio for reuse
drm/i915/dp_mst: Limit M/N ratio for MST
drm/i915/dp: Add M/N ratio check for DP link config
drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
drm/i915/display_wa: Add support for Wa_14021768792
drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
ratio > 10
drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass
Suraj Kandpal (3):
drm/i915/dp: Limit M/N ratio for DP
drm/i915/display_wa: Add support for Wa_14014191401
drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 113 +++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 4 +
.../gpu/drm/i915/display/intel_display_regs.h | 12 ++
.../drm/i915/display/intel_display_types.h | 2 +
.../gpu/drm/i915/display/intel_display_wa.c | 11 ++
.../gpu/drm/i915/display/intel_display_wa.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 167 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.h | 6 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +
10 files changed, 321 insertions(+), 9 deletions(-)
--
2.34.1
