Since this mask is only used in conjunction with RPS, move it alongside
its brethen in the i915->rps struct.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++-----------
3 files changed, 29 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e8e532dcf136..3461b9838013 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -963,6 +963,7 @@ struct intel_gen6_power_mgmt {
/* work and pm_iir are protected by dev_priv->irq_lock */
struct work_struct work;
u32 pm_iir;
+ u32 pm_events;
/* Frequencies are stored in potentially platform dependent multiples.
* In other words, *_freq needs to be multiplied by X to be interesting.
@@ -1486,7 +1487,6 @@ struct drm_i915_private {
};
u32 gt_irq_mask;
u32 pm_irq_mask;
- u32 pm_rps_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct delayed_work hotplug_work;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9c72d26f1066..973dd03a21e5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1336,17 +1336,16 @@ static void gen6_pm_rps_work(struct work_struct *work)
pm_iir = dev_priv->rps.pm_iir;
dev_priv->rps.pm_iir = 0;
if (INTEL_INFO(dev_priv->dev)->gen >= 8)
- gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- else {
+ gen8_enable_pm_irq(dev_priv, dev_priv->rps.pm_events);
+ else
/* Make sure not to corrupt PMIMR state used by ringbuffer */
- gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- }
+ gen6_enable_pm_irq(dev_priv, dev_priv->rps.pm_events);
spin_unlock_irq(&dev_priv->irq_lock);
/* Make sure we didn't queue anything we're not going to process. */
- WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
+ WARN_ON(pm_iir & ~dev_priv->rps.pm_events);
- if ((pm_iir & dev_priv->pm_rps_events) == 0)
+ if ((pm_iir & dev_priv->rps.pm_events) == 0)
return;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -1549,12 +1548,12 @@ static void snb_gt_irq_handler(struct drm_device *dev,
static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
{
- if ((pm_iir & dev_priv->pm_rps_events) == 0)
+ if ((pm_iir & dev_priv->rps.pm_events) == 0)
return;
spin_lock(&dev_priv->irq_lock);
- dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
- gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
+ dev_priv->rps.pm_iir |= pm_iir & dev_priv->rps.pm_events;
+ gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->rps.pm_events);
spin_unlock(&dev_priv->irq_lock);
queue_work(dev_priv->wq, &dev_priv->rps.work);
@@ -1617,9 +1616,9 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev,
if (master_ctl & GEN8_GT_PM_IRQ) {
tmp = I915_READ(GEN8_GT_IIR(2));
- if (tmp & dev_priv->pm_rps_events) {
+ if (tmp & dev_priv->rps.pm_events) {
I915_WRITE(GEN8_GT_IIR(2),
- tmp & dev_priv->pm_rps_events);
+ tmp & dev_priv->rps.pm_events);
ret = IRQ_HANDLED;
gen8_rps_irq_handler(dev_priv, tmp);
} else
@@ -1944,10 +1943,10 @@ void gen8_flip_interrupt(struct drm_device *dev)
* the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
{
- if (pm_iir & dev_priv->pm_rps_events) {
+ if (pm_iir & dev_priv->rps.pm_events) {
spin_lock(&dev_priv->irq_lock);
- dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
- gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
+ dev_priv->rps.pm_iir |= pm_iir & dev_priv->rps.pm_events;
+ gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->rps.pm_events);
spin_unlock(&dev_priv->irq_lock);
queue_work(dev_priv->wq, &dev_priv->rps.work);
@@ -3537,7 +3536,7 @@ static void gen5_gt_irq_postinstall(struct drm_device
*dev)
GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
if (INTEL_INFO(dev)->gen >= 6) {
- pm_irqs |= dev_priv->pm_rps_events;
+ pm_irqs |= dev_priv->rps.pm_events;
if (HAS_VEBOX(dev))
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
@@ -3742,7 +3741,7 @@ static void gen8_gt_irq_postinstall(struct
drm_i915_private *dev_priv)
dev_priv->pm_irq_mask = 0xffffffff;
GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
- GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask,
dev_priv->pm_rps_events);
+ GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask,
dev_priv->rps.pm_events);
GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
@@ -4597,9 +4596,9 @@ void intel_irq_init(struct drm_device *dev)
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
/* WaGsvRC0ResidenncyMethod:VLV */
- dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED;
+ dev_priv->rps.pm_events = GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED;
else
- dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+ dev_priv->rps.pm_events = GEN6_PM_RPS_EVENTS;
setup_timer(&dev_priv->gpu_error.hangcheck_timer,
i915_hangcheck_elapsed,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70f6d9c392c4..9903073ec5a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3348,7 +3348,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (val < dev_priv->rps.max_freq_softlimit)
mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
- mask &= dev_priv->pm_rps_events;
+ mask &= dev_priv->rps.pm_events;
/* IVB and SNB hard hangs on looping batchbuffer
* if GEN6_PM_UP_EI_EXPIRED is masked.
@@ -3451,7 +3451,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
{
mutex_lock(&dev_priv->rps.hw_lock);
if (dev_priv->rps.enabled) {
- if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED))
+ if (dev_priv->rps.pm_events & (GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED))
gen6_rps_reset_ei(dev_priv);
I915_WRITE(GEN6_PMINTRMSK,
gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
@@ -3551,8 +3551,8 @@ static void gen8_disable_rps_interrupts(struct drm_device
*dev)
dev_priv-> rps.is_bdw_sw_turbo = false;
} else {
I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
- I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
- ~dev_priv->pm_rps_events);
+ I915_WRITE(GEN8_GT_IER(2),
+ I915_READ(GEN8_GT_IER(2)) &
~dev_priv->rps.pm_events);
/* Complete PM interrupt masking here doesn't race with the rps
work
* item again unmasking PM interrupts because that is using a
different
* register (GEN8_GT_IMR(2)) to mask PM interrupts. The only
risk is in
@@ -3563,7 +3563,7 @@ static void gen8_disable_rps_interrupts(struct drm_device
*dev)
dev_priv->rps.pm_iir = 0;
spin_unlock_irq(&dev_priv->irq_lock);
- I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
+ I915_WRITE(GEN8_GT_IIR(2), dev_priv->rps.pm_events);
}
}
@@ -3573,7 +3573,7 @@ static void gen6_disable_rps_interrupts(struct drm_device
*dev)
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
- ~dev_priv->pm_rps_events);
+ ~dev_priv->rps.pm_events);
/* Complete PM interrupt masking here doesn't race with the rps work
* item again unmasking PM interrupts because that is using a different
* register (PMIMR) to mask PM interrupts. The only risk is in leaving
@@ -3583,7 +3583,7 @@ static void gen6_disable_rps_interrupts(struct drm_device
*dev)
dev_priv->rps.pm_iir = 0;
spin_unlock_irq(&dev_priv->irq_lock);
- I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
+ I915_WRITE(GEN6_PMIIR, dev_priv->rps.pm_events);
}
static void gen6_disable_rps(struct drm_device *dev)
@@ -3687,8 +3687,8 @@ static void gen8_enable_rps_interrupts(struct drm_device
*dev)
spin_lock_irq(&dev_priv->irq_lock);
WARN_ON(dev_priv->rps.pm_iir);
- gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
+ gen8_enable_pm_irq(dev_priv, dev_priv->rps.pm_events);
+ I915_WRITE(GEN8_GT_IIR(2), dev_priv->rps.pm_events);
spin_unlock_irq(&dev_priv->irq_lock);
}
@@ -3698,8 +3698,8 @@ static void gen6_enable_rps_interrupts(struct drm_device
*dev)
spin_lock_irq(&dev_priv->irq_lock);
WARN_ON(dev_priv->rps.pm_iir);
- gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
+ gen6_enable_pm_irq(dev_priv, dev_priv->rps.pm_events);
+ I915_WRITE(GEN6_PMIIR, dev_priv->rps.pm_events);
spin_unlock_irq(&dev_priv->irq_lock);
}
--
2.1.0
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