On Fri, Dec 16, 2016 at 02:36:57AM +0000, Stuart Yoder wrote: > For context, please see the thread: > https://www.spinics.net/lists/arm-kernel/msg539066.html > > The existing iommu-map binding did not account for the situation where > #iommu-cells == 2, as permitted in the ARM SMMU binding. The 2nd cell > of the IOMMU specifier being the SMR mask. The existing binding defines > the mapping as: > Any RID r in the interval [rid-base, rid-base + length) is associated with > the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base). > > ...and that does not work if iommu-base is 2 cells, the second being the > SMR mask. > > While this can be worked around by always having length=1, it seems we > can get this cleaned up by updating the binding definition for iommu-map.
To reiterate, I'm very much not keen on the pci-iommu binding having knowledge of the decomposition of iommu-specifiers from other bindings. As mentioned previously, there's an intended interpretation [1] that we need to fix up the pci-iommu binding with. With that, I don't think it's even necessary to bodge iommu-cells = <1> AFAICT. I'm sorry that the patch I suggested never materialized; let me figure out the wording now... Thanks, Mark. [1] https://www.spinics.net/lists/arm-kernel/msg539357.html > > See patch below. Thoughts? > > Thanks, > Stuart > > ------------------------------------------------------------------------- > > diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.txt > b/Documentation/devicetree/bindings/pci/pci-iommu.txt > index 56c8296..e81b461 100644 > --- a/Documentation/devicetree/bindings/pci/pci-iommu.txt > +++ b/Documentation/devicetree/bindings/pci/pci-iommu.txt > @@ -38,8 +38,20 @@ Optional properties > The property is an arbitrary number of tuples of > (rid-base,iommu,iommu-base,length). > > - Any RID r in the interval [rid-base, rid-base + length) is associated with > - the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base). > + If the associated IOMMU has an #iommu-cells value of 1, any RID r in the > + interval [rid-base, rid-base + length) is associated with the listed IOMMU, > + with the iommu-specifier (r - rid-base + iommu-base). > + > + ARM SMMU Note: > + The ARM SMMU binding permits an #iommu-cells value of 2 and in this > + case defines an IOMMU specifier to be: (stream-id,smr-mask) > + > + In an iommu-map this means the iommu-base consists of 2 cells: > + (rid-base,iommu,[stream-id,smr-mask],length). > + > + In this case the RID to IOMMU specifier mapping is defined to be: > + any RID r in the interval [rid-base, rid-base + length) is associated > + with the listed IOMMU, with the iommu-specifier (r - rid-base + > stream-id). > > - iommu-map-mask: A mask to be applied to each Requester ID prior to being > mapped to an iommu-specifier per the iommu-map property. > > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
