Thanks for the information, I have been looking more into this thread.
For my understanding:
Is the pci_(read/write)_config() access using MMIO from guest ARM side
supposed to access .pci_mmconfig_base address (0xfc000000 for zcu102, which
I see it being "reserved memory" in the Ultrascale+ TRM) and thus
trigger arch_handle_dabt()->mmio_handle_access() on hypervisor side, or am
I off track?


On Wed, Aug 9, 2017 at 4:23 PM, Henning Schild <henning.sch...@siemens.com>

> Hey,
> unfortunately Jonas never published his overall changes, maybe now he
> understands why i kindly asked him to do so.
> I think Jonas maybe ran into every single problem one could encounter
> on the way, so if you read the thread you will probably be able to come
> up with a similar patch at some point. That would be the duplication of
> efforts, getting a first working patch into a mergeable form is another
> story.
> If there are legal reasons to not publish code on the list i suggest
> you exchange patches between each other. But of cause i would like to
> see contributions eventually ;).
> regards,
> Henning
> Am Tue, 8 Aug 2017 00:27:31 -0700
> schrieb Constantin Petra <constantin.pe...@gmail.com>:
> > Hi,
> >
> > Sorry to pick this up after this time, but I would be interested in
> > the pci.c modifications related to ARM for inmates (using MMIO
> > instead of PIO). Was there a follow-up to the discussions
> > above?(checked out the discussion archives but I can't find any). I
> > would like to avoid re-inventing the wheel if there's one already
> > rolling.
> >
> > Thanks,
> > Constantin

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