On 2017-08-10 08:33, Constantin Petra wrote:
> Thanks for the information, I have been looking more into this thread.
> For my understanding:
> Is the pci_(read/write)_config() access using MMIO from guest ARM side
> supposed to access .pci_mmconfig_base address (0xfc000000 for zcu102,
> which I see it being "reserved memory" in the Ultrascale+ TRM) and thus
> trigger arch_handle_dabt()->mmio_handle_access() on hypervisor side, or
> am I off track?
Nope, that's how things are supposed to work on that board. The MMIO
config space is fully virtualized, so we picked an unused address range
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux
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