On 11.06.19 01:03, Ralf Ramsauer wrote:
Add R/W accessors for CR3, CR4, XCR0 and implement CPUID.
Partly copied over from the hypervisor and added cpuid_edax helper,
which combines edx:eax to a 64 bit uint.
The bits you copied over, who has copyright on them? If it was only you and some
folks from Siemens, this is fine, but it should still be documented.
And use these acessors where it's already possible.
accessors
Jan
Signed-off-by: Ralf Ramsauer <[email protected]>
---
inmates/lib/x86/include/asm/regs.h | 79 ++++++++++++++++++++++++++++++
inmates/lib/x86/mem.c | 3 +-
2 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/inmates/lib/x86/include/asm/regs.h
b/inmates/lib/x86/include/asm/regs.h
index a004fdd2..cfea8580 100644
--- a/inmates/lib/x86/include/asm/regs.h
+++ b/inmates/lib/x86/include/asm/regs.h
@@ -48,3 +48,82 @@
#define MSR_MTRR_DEF_TYPE 0x000002ff
#define MTRR_ENABLE 0x00000800
+
+#ifndef __ASSEMBLY__
+
+#include <string.h>
+
+static unsigned long __force_order;
+
+#define READ_CR(n) \
+ static inline unsigned long read_cr##n(void) \
+ { \
+ unsigned long cr; \
+ asm volatile("mov %%cr" __stringify(n) ", %0" \
+ : "=r" (cr), "=m" (__force_order)); \
+ \
+ return cr; \
+ }
+
+READ_CR(3)
+READ_CR(4)
+
+static inline void write_cr4(unsigned long val)
+{
+ asm volatile("mov %0, %%cr4" : : "r" (val), "m" (__force_order));
+}
+
+static inline u64 read_xcr0(void)
+{
+ register u32 eax, edx;
+
+ asm volatile("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
+
+ return ((u64)(edx) << 32) + ((u64)(eax));
+}
+
+static inline void write_xcr0(u64 xcr0)
+{
+ unsigned int eax = xcr0;
+ unsigned int edx = xcr0 >> 32;
+
+ asm volatile("xsetbv" : : "a" (eax), "d" (edx), "c" (0));
+}
+
+static inline void cpuid(unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ /* ecx is often an input as well as an output. */
+ asm volatile("cpuid"
+ : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
+}
+
+static inline u64 cpuid_edax(unsigned int op, unsigned int sub)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ eax = op;
+ ecx = sub;
+ cpuid(&eax, &ebx, &ecx, &edx);
+ return ((u64)edx << 32) + (u64)eax;
+}
+
+#define CPUID_REG(reg) \
+static inline unsigned int cpuid_##reg(unsigned int op, unsigned int sub) \
+{ \
+ unsigned int eax, ebx, ecx, edx; \
+ \
+ eax = op; \
+ ecx = sub; \
+ cpuid(&eax, &ebx, &ecx, &edx); \
+ return reg; \
+}
+
+CPUID_REG(eax)
+CPUID_REG(ebx)
+CPUID_REG(ecx)
+CPUID_REG(edx)
+
+#endif /* __ASSEMBLY__ */
diff --git a/inmates/lib/x86/mem.c b/inmates/lib/x86/mem.c
index c6903897..e391f2b0 100644
--- a/inmates/lib/x86/mem.c
+++ b/inmates/lib/x86/mem.c
@@ -37,6 +37,7 @@
*/
#include <inmate.h>
+#include <asm/regs.h>
#define PG_PRESENT 0x01
#define PG_RW 0x02
@@ -48,7 +49,7 @@ void map_range(void *start, unsigned long size, enum map_type
map_type)
unsigned long pt_addr, *pt_entry, *pt;
unsigned long vaddr = (unsigned long)start;
- asm volatile("mov %%cr3,%0" : "=r" (pt_addr));
+ pt_addr = read_cr3();
size += (vaddr & ~HUGE_PAGE_MASK) + HUGE_PAGE_SIZE - 1;
size &= HUGE_PAGE_MASK;
--
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