Hello, I have been paying with jailhouse in a UltraZed SoM with AES-ZU-IOCC-G carrier card from avnet. So far, I have been able to enable the root cell, create a aremetal cell where I was able to load the baremetal examples like gic-demo and a custom one where I was able to turn on some leds via axi gpio in PL side.
Now I'm trying to run an example where I can catch the interrupt from an axi gpio in PL and I am not able to do that. I'm using PL to PS interrupts in my design and the signal is being generated. I also tested with Xilinx SDK. I tried with PS to PL group 0 and group 1. Irq numbers 121 and 136 and no success. I don't know what I'm missing. I attach the cells and the demo source. Any help would be appreciated. Thanks in advance. Alex -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/CANdaEOi5f13kg0OF%2B6iYrzmoJUTOhtgu4%3Dr%2B0Vt%2BZQ4oTtf1DQ%40mail.gmail.com. For more options, visit https://groups.google.com/d/optout.
/* * Jailhouse, a Linux-based partitioning hypervisor * * Configuration for gic-demo inmate on Xilinx ZynqMP ZCU102 eval board: * 1 CPU, 64K RAM, 1 serial port * * Copyright (c) Siemens AG, 2016 * * Authors: * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> struct { struct jailhouse_cell_desc cell; __u64 cpus[1]; struct jailhouse_memory mem_regions[5]; } __attribute__((packed)) config = { .cell = { .signature = JAILHOUSE_CELL_DESC_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .name = "gpio-leds-demo", .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = 0, .pio_bitmap_size = 0, .num_pci_devices = 0, .console = { .address = 0xff010000, .type = JAILHOUSE_CON_TYPE_XUARTPS, .flags = JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4, }, }, .cpus = { 0x8, }, .mem_regions = { /* UART */ { .phys_start = 0xff010000, .virt_start = 0xff010000, .size = 0x1000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* RAM */ { .phys_start = 0x42000000, .virt_start = 0, .size = 0x00010000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, }, /* GPIO_SWITCHES */ { .phys_start = 0x80000000, .virt_start = 0x80000000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* GPIO_LEDS */ { .phys_start = 0x80001000, .virt_start = 0x80001000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* communication region */ { .virt_start = 0x80000000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_COMM_REGION, }, } };
/* * Jailhouse, a Linux-based partitioning hypervisor * * Configuration for Xilinx ZynqMP ZCU102 eval board * * Copyright (c) Siemens AG, 2016 * * Authors: * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. * * Reservation via device tree: 0x800000000..0x83fffffff */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> //#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) struct { struct jailhouse_system header; __u64 cpus[1]; struct jailhouse_memory mem_regions[8]; struct jailhouse_irqchip irqchips[1]; } __attribute__((packed)) config = { .header = { .signature = JAILHOUSE_SYSTEM_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, .hypervisor_memory = { .phys_start = 0x40000000, .size = 0x01000000, }, .debug_console = { .address = 0xff000000, .size = 0x1000, .type = JAILHOUSE_CON_TYPE_XUARTPS, .flags = JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4, }, .platform_info = { .pci_mmconfig_base = 0xfc000000, .pci_mmconfig_end_bus = 0, .pci_is_virtual = 1, .pci_domain = -1, .arm = { .gic_version = 2, .gicd_base = 0xf9010000, .gicc_base = 0xf902f000, .gich_base = 0xf9040000, .gicv_base = 0xf906f000, .maintenance_irq = 25, }, }, .root_cell = { .name = "UltraZed SoM ehu", .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), .vpci_irq_base = 136-32, }, }, .cpus = { 0xf, }, .mem_regions = { /* MMIO (permissive) */ { .phys_start = 0xfd000000, .virt_start = 0xfd000000, .size = 0x03000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* RAM */ { .phys_start = 0x0, .virt_start = 0x0, .size = 0x40000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, /* RAM */ { .phys_start = 0x42000000, .virt_start = 0x42000000, .size = 0x3e000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, /* PL gpio switches */ { .phys_start = 0x80000000, .virt_start = 0x80000000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* PL gpio leds */ { .phys_start = 0x80001000, .virt_start = 0x80001000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* IVSHMEM shared memory region for 00:00.0 */ { .phys_start = 0x41400000, .virt_start = 0x41400000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, /* IVSHMEM shared memory region for 00:01.0 */ { .phys_start = 0x41500000, .virt_start = 0x41500000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, }, .irqchips = { /* GIC */ { .address = 0xf9010000, .pin_base = 32, .pin_bitmap = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, }, }, }, };
/* * Jailhouse, a Linux-based partitioning hypervisor * * Copyright (c) ARM Limited, 2014 * Copyright (c) Siemens AG, 2014-2017 * * Authors: * Jean-Philippe Brucker <[email protected]> * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. */ #include <inmate.h> #include <gic.h> #define GPIO_IRQ_NUM 136 #define GPIO_LEDS_BASE_ADDRESS 0x80001000 #define GPIO_SWITCH_BASE_ADDRESS 0x80000000 static void handle_IRQ(unsigned int irqn) { if (irqn != GPIO_IRQ_NUM) return; printk("Switch changed\n"); } void inmate_main(void) { unsigned int *p_gpio_leds = (unsigned int *)GPIO_LEDS_BASE_ADDRESS; unsigned int *p_gpio_switch = (unsigned int *)GPIO_SWITCH_BASE_ADDRESS; printk("Initializing the GIC for GPIO IRQ...\n"); mmio_write32(p_gpio_leds , 0xA5); //Some leds on mmio_write32((p_gpio_switch + 0x4), 0xFF); //All inputs in gpio mmio_write32((p_gpio_switch + 0x128), 0x1); //Enable channel 1 irq mmio_write32((p_gpio_switch + 0x11C), 0x80000000); //Enable global irq gic_setup(handle_IRQ); gic_enable_irq(GPIO_IRQ_NUM); halt(); }
