Thanks for the reply. It really pointed me in the right way.
The inmate didn't crash when issuing the first mmio access, but it was
because I had overlapping memory regions.
My AXI GPIO address was the same as the communication area.
I changed the hardware design in Vivado to get different addresses and
then, as you said, I needed the "map_range" call.
It all worked as expected now.
Thank you very much.
El sábado, 20 de julio de 2019, 4:44:56 (UTC+2), Jan Kiszka escribió:
>
> On 20.07.19 00:58, Alejandro Largacha wrote:
> > I just tried and did not work. I don't know what I'm missing
> > I attach the config and the demo code
> >
>
> Config looks good, but your inmate should crash when issuing the first
> mmio
> accesses because you didn't map them into the inmate address space. Try
> adding
>
> map_range(GPIO_SWITCH_BASE_ADDRESS, 0x2000, MAP_UNCACHED);
>
> before the first access.
>
> Jan
>
> > El viernes, 19 de julio de 2019, 7:08:41 (UTC+2), Jan Kiszka escribió:
> >
> > On 19.07.19 01:32, Alejandro Largacha wrote:
> > > Hello,
> > >
> > > Thank you very much for the reply. I tried adding the irqchip
> entry to the
> > cell config but no success. I have a doubt about the pin_bitmap
> entry. Is it
> > divided in 4 groups of 32 bits? Then, how should be the entry like
> for the
> > irq num 136. Like this?
> > >
> > > .irqchips = {
> > > /* GIC */ {
> > > .address = 0xf9010000,
> > > .pin_base = 32,
> >
> > This means bit 0 in the first word of pin_bitmap encodes GIC
> interrupt 32.
> > Then,
> > when that bit is set, permission is granted.
> >
> > > .pin_bitmap = {
> > > 1 << (54 - 32),
> >
> > So this one grants access to GIC int 54 - not sure if you need that.
> >
> > > 0,
> > > 0,
> > > 1 << (136 - 128)
> >
> > And this permits access to int 136 because this 4th word controls
> interrupts
> > 128-159.
> >
> > Did you already try out the config?
> >
> > Jan
> >
> > > },
> > > },
> > > }
> > >
> > >
> > > I attach my new cell config file.
> > >
> > > El miércoles, 10 de julio de 2019, 7:20:56 (UTC+2), Jan Kiszka
> escribió:
> > >> On 10.07.19 06:57, Alejandro Largacha wrote:
> > >>> Hello,
> > >>>
> > >>> I have been paying with jailhouse in a UltraZed SoM with
> AES-ZU-IOCC-G
> > carrier
> > >>> card from avnet.
> > >>> So far, I have been able to enable the root cell, create a
> aremetal cell
> > where I
> > >>> was able to load the baremetal
> > >>> examples like gic-demo and a custom one where I was able to turn
> on some
> > leds
> > >>> via axi gpio in PL side.
> > >>>
> > >>> Now I'm trying to run an example where I can catch the interrupt
> from an
> > axi
> > >>> gpio in PL and I am not able to do that.
> > >>> I'm using PL to PS interrupts in my design and the signal is
> being
> > generated. I
> > >>> also tested with Xilinx SDK.
> > >>> I tried with PS to PL group 0 and group 1. Irq numbers 121 and
> 136 and no
> > >>> success. I don't know what I'm missing.
> > >>> I attach the cells and the demo source.
> > >>>
> > >>
> > >> Your baremetal cell config is not permitting the cell access to
> the GIC
> > >> interrupt 136 you are using. Replicate the irqchip entry and
> create bitmask
> > >> where only bit 136 - 32 (32 is the base) is set. See also other
> examples
> > >> in-tree, including those for the zcu102 or the ultra96. Both
> grant their
> > >> non-root linux cells access to certain interrupts.
> > >>
> > >> Jan
> > >>
> > >> --
> > >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> > >> Corporate Competence Center Embedded Linux
> > >
> >
> > --
> > Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> > Corporate Competence Center Embedded Linux
> >
> > --
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