I just tried and did not work. I don't know what I'm missing
I attach the config and the demo code
El viernes, 19 de julio de 2019, 7:08:41 (UTC+2), Jan Kiszka escribió:
>
> On 19.07.19 01:32, Alejandro Largacha wrote:
> > Hello,
> >
> > Thank you very much for the reply. I tried adding the irqchip entry to
> the cell config but no success. I have a doubt about the pin_bitmap entry.
> Is it divided in 4 groups of 32 bits? Then, how should be the entry like
> for the irq num 136. Like this?
> >
> > .irqchips = {
> > /* GIC */ {
> > .address = 0xf9010000,
> > .pin_base = 32,
>
> This means bit 0 in the first word of pin_bitmap encodes GIC interrupt 32.
> Then,
> when that bit is set, permission is granted.
>
> > .pin_bitmap = {
> > 1 << (54 - 32),
>
> So this one grants access to GIC int 54 - not sure if you need that.
>
> > 0,
> > 0,
> > 1 << (136 - 128)
>
> And this permits access to int 136 because this 4th word controls
> interrupts
> 128-159.
>
> Did you already try out the config?
>
> Jan
>
> > },
> > },
> > }
> >
> >
> > I attach my new cell config file.
> >
> > El miércoles, 10 de julio de 2019, 7:20:56 (UTC+2), Jan Kiszka
> escribió:
> >> On 10.07.19 06:57, Alejandro Largacha wrote:
> >>> Hello,
> >>>
> >>> I have been paying with jailhouse in a UltraZed SoM with AES-ZU-IOCC-G
> carrier
> >>> card from avnet.
> >>> So far, I have been able to enable the root cell, create a aremetal
> cell where I
> >>> was able to load the baremetal
> >>> examples like gic-demo and a custom one where I was able to turn on
> some leds
> >>> via axi gpio in PL side.
> >>>
> >>> Now I'm trying to run an example where I can catch the interrupt from
> an axi
> >>> gpio in PL and I am not able to do that.
> >>> I'm using PL to PS interrupts in my design and the signal is being
> generated. I
> >>> also tested with Xilinx SDK.
> >>> I tried with PS to PL group 0 and group 1. Irq numbers 121 and 136 and
> no
> >>> success. I don't know what I'm missing.
> >>> I attach the cells and the demo source.
> >>>
> >>
> >> Your baremetal cell config is not permitting the cell access to the GIC
> >> interrupt 136 you are using. Replicate the irqchip entry and create
> bitmask
> >> where only bit 136 - 32 (32 is the base) is set. See also other
> examples
> >> in-tree, including those for the zcu102 or the ultra96. Both grant
> their
> >> non-root linux cells access to certain interrupts.
> >>
> >> Jan
> >>
> >> --
> >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> >> Corporate Competence Center Embedded Linux
> >
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>
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/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for gic-demo inmate on Xilinx ZynqMP ZCU102 eval board:
* 1 CPU, 64K RAM, 1 serial port
*
* Copyright (c) Siemens AG, 2016
*
* Authors:
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[5];
struct jailhouse_irqchip irqchips[1];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "gpio-leds-demo",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.pio_bitmap_size = 0,
.num_pci_devices = 0,
.console = {
.address = 0xff010000,
.type = JAILHOUSE_CON_TYPE_XUARTPS,
.flags = JAILHOUSE_CON_ACCESS_MMIO |
JAILHOUSE_CON_REGDIST_4,
},
},
.cpus = {
0x8,
},
.mem_regions = {
/* UART */ {
.phys_start = 0xff010000,
.virt_start = 0xff010000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* RAM */ {
.phys_start = 0x42000000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* GPIO_SWITCHES */ {
.phys_start = 0x80000000,
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* GPIO_LEDS */ {
.phys_start = 0x80001000,
.virt_start = 0x80001000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* communication region */ {
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.irqchips = {
/* GIC */ {
.address = 0xf9010000,
.pin_base = 32,
.pin_bitmap = {
1 << (54 - 32),
0,
0,
1 << (136 - 128)
},
},
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) ARM Limited, 2014
* Copyright (c) Siemens AG, 2014-2017
*
* Authors:
* Jean-Philippe Brucker <[email protected]>
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <inmate.h>
#include <gic.h>
#define GPIO_IRQ_NUM 136
#define GPIO_LEDS_BASE_ADDRESS 0x80001000
#define GPIO_SWITCH_BASE_ADDRESS 0x80000000
static void handle_IRQ(unsigned int irqn)
{
if (irqn != GPIO_IRQ_NUM)
return;
printk("Button pressed\n");
}
void inmate_main(void)
{
char *p_gpio_leds = (char *)GPIO_LEDS_BASE_ADDRESS;
char *p_gpio_switch = (char *)GPIO_SWITCH_BASE_ADDRESS;
printk("Initializing the GIC for GPIO IRQ...\n");
mmio_write32(p_gpio_leds , 0xA5);
/* AXI GPIO IRQ config */
mmio_write32((p_gpio_switch + 0x4), 0xFF); /* All inputs */
mmio_write32((p_gpio_switch + 0x128), 0x1); /* Enable channel 1 interrupts */
mmio_write32((p_gpio_switch + 0x11C), 0x80000000); /* Enable global interrupt */
gic_setup(handle_IRQ);
gic_enable_irq(GPIO_IRQ_NUM);
halt();
}
