Status: Assigned
Owner: sebastien.lelong
Labels: Type-Defect Priority-Medium
New issue 140 by sebastien.lelong: ADC & voltage configuration support for
18F4620 (using PCFG *and* VCFG bits)
http://code.google.com/p/jallib/issues/detail?id=140
Noel says voltage configuration for 18f4620 is performed through VCFG bits,
while configuring analog pins is done through PCFG bits.
This case isn't handle by current adc_channels.jal library ,which assumes
when PCFG bits are used to configure depending analog channels, then Vref
config is also done using this PCFG bits. This is what you usually see when
looking at PCFG table, some cells have "Vref+" or "Vref-".
So, there seems to be another case, a fourth case, to be implemented in
adc_channels. For the record:
-- -----------------------------------------
-- FIRST CASE:
-- - PCFG bits exist,
-- - analog are dependent from each other
-- - Vref config is done via PCFG bits
-- combination
-- -----------------------------------------
-- --------------------------------------------
-- SECOND CASE:
-- - PCFG bits exist
-- - analog are independent from each other
-- - Vref config is done via VCFG bits
-- --------------------------------------------
-- --------------------------------------------
-- THIRD CASE:
-- - ANS bits exist,
-- - analog are independent from each other
-- - Vref config is done via VCFG bits
-- --------------------------------------------
--
You received this message because you are subscribed to the Google Groups
"jallib" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/jallib?hl=en.
