Comment #2 on issue 140 by sebastien.lelong: ADC & voltage configuration
support for 18F4620 (using PCFG *and* VCFG bits)
http://code.google.com/p/jallib/issues/detail?id=140
Hi again on this topic,
ADC_NVREF = 0, handled via VCFG/ADREF/ADPREF-ADNREF bits, doesn't set any
bits and leaves default POR values. According to datasheet, these bits
equal 0 on POR, so no external Vref configured. It has worked for the many
handled & testes chips, though, as reported by Arcady, ADC_NVREF = 0
resulting configuration should be handled explicitely.
What you, Rob, report about enable_digital_io() is interesting as it seems
to explain why these bits don't follow default values with 16f1827. I'm
suspecting a bug in this procedure. Shouldn't it touch these bits and let
them at their default values, as in other chips ?
TIA
Seb
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