Comment #5 on issue 140 by sebastien.lelong: ADC & voltage configuration
support for 18F4620 (using PCFG *and* VCFG bits)
http://code.google.com/p/jallib/issues/detail?id=140
Hi Rob,
I don't understand: what did you change ? Except explicitely settings bits
to mach no Vref setting, am I supposed to change something else in ADC
libs ? Do you think what you described is a bug ?
cheers,
seb
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