On Wed, Oct 21, 2009 at 4:58 PM, David <[email protected]> wrote: > > Hi, > I read a lot of posts in this forum about ERC errors produced by EESchema ERC > function. Why do people waste so much time trying to find out why EESchema > produces these errors instead of relying on basic electrical first > principles? When I'm drawing a schematic I set all pins that cause me > problems (in EESchema) to passive. Instead I rely on a thorough study of any > device data sheets and Kirchoffs laws/electrical principles. I can understand > if someone has not had any electronics training/experience but surely the > designer of the circuit, i.e you, have a better understanding of how things > should be connected. > Sorry for the rant. > > David.
David: I agree that the built-in KiCad ERC is pretty minimal, but that doesn't mean that ERC is a waste of time. For years, I have programmatically done ERC on netlists between OrCad and PADs. I am working on porting that checking to Kicad, but in a more board-independent way than I have done in the past. (Historically, I code up a board-specific checker for every board.) So far, for KiCad, I have some ERC functions that look at really basic stuff. They can catch some errors the built-in ERC doesn't. But I haven't yet ported the "big guns" which will look at bus connectivity, pullups/pulldowns/series terminations, etc. (The current checker is available at kipy.org.) You may think that ERC is useless, and I agree that saying something is a "power pin" without saying whether it is 3.3V or 5V or 12V or even (on phone line stuff I work on for my employer) +80V or -60V is suboptimal. An ERC which says "OK" when you connect a +3.3V logic power pin to -60V battery does not give me a warm fuzzy. But it is possible to describe components to an ERC more descriptively, such that the results are more useful. This may not be worthwhile on a small board, but trust me -- when I have a board with two 1500 pin FPGAs on it, it is very useful to insure that each I/O pin is connected to a bank with the correct VIO voltage, and this is not something I want to recheck manually after each of 200 schematic edits. And it is very possible to catch many of the sorts of errors humans make. Is a signal named "fred" on one sheet and "freddy" on another? Checking that global labels are used on more than one page can help catch this. Checking to see if a global label is used more than once on a page can help save you from cut and paste errors. Checking to see that all pins are connected properly to nets (or have Xs on them) can help save you from slight alignment errors on the schematic sheet. My ERC will do all these things, and the built-in one will do some of them. Should a human being still peruse the schematic? You bet. But computers can and should be programmed to relieve some of the tedium, and report some of the schematic details in a tabular form which lends itself to deeper global inspection by said human. Regards, Pat
