Hi, I can answer that in a few separate parts: 1) Most user's trouble, specilly begginers, is about Power-in and Power-out. That got me too in the beggining... I was used t another CAD that had just "Power" so the PWR_FLG problem did not appear. Kicad's way is conceptualy better but I doubt if this really will actch a single extra error.
2) ERC messages are very hard to undestand, particularly for the case above. apart from being cpyptical, it is often in the wrong page. Maybe a suggestion is to show all connections aon all pages related to that error. 3) Small error like an overlap instead of a connection are hard to find, but with time it gets easyer... A good suggestion would be to indicate overlaps with a differente color. Alain David escreveu: > Hi, > I read a lot of posts in this forum about ERC errors produced by EESchema ERC > function. Why do people waste so much time trying to find out why EESchema > produces these errors instead of relying on basic electrical first > principles? When I'm drawing a schematic I set all pins that cause me > problems (in EESchema) to passive. Instead I rely on a thorough study of any > device data sheets and Kirchoffs laws/electrical principles. I can understand > if someone has not had any electronics training/experience but surely the > designer of the circuit, i.e you, have a better understanding of how things > should be connected. > Sorry for the rant. > > David. >
