Very interesting .. Robert wrote: > I often have to work with MLF/QFN devices, which have a thermal pad on > the bottom. There are two considerations here. Firstly there is the > heatsinking requirement, and secondly if you get the copper design wrong > the chip will float on a central blob of solder, resulting in unreliable > soldering of the pins. > > For the thermal pad footprint for a 32 pin device I arrange 8 square > pads around a central via, and I place solder resist over the via.
Do you mean 9 pads instead of 8? (A picture would be worth a thousand words here) .. > I connect together the pads and the via with a grid of thick tracks. The tracks cover the thermal pattern generation? > The use of a tented via in this way means that the > via will be solidly connected to the heatsinking copper zone on the > reverse side, whilst the tenting prevents solder wicking through the > via. I'm not sure I understand exactly -- do you mean the solder sicking would move enough solder to float the chip? I'm thinking you might mean that the pads break up the area ( sort of a star shaped area) so with smaller blobs the chip floats less? I can see the use of tracks or a small copper pour area with thermals turned off to deal with prevention of thermal necking, but I think in the end there should be a no-thermal attribute for a pad definition. I started writing this up at: http://wiki.xtronics.com/index.php/Pcbnew#Preventing_Thermals_on_heatsinking_pads_of_SM_packages -------------------------------------------------------------------------------- Karl Schmidt EMail [email protected] Transtronics, Inc. WEB http://xtronics.com 3209 West 9th Street Ph (785) 841-3089 Lawrence, KS 66049 FAX (785) 841-0434 Age is an issue of mind over matter. If you don't mind, it doesn't matter. -- Mark Twain --------------------------------------------------------------------------------
