From: "Paul G. Allen" <[EMAIL PROTECTED]>
This reminds me of the Ti 99 series of CPUs. They were stackless and had
a memory-to-memory architecture. They only had three hardware registers
- program counter, status register, and workspace pointer. With these
chips, a context switch was up to 4 times faster than on the x86 running
at the same clock speed. A complete context switch could be performed
with a single instruction, and the limiting factor on the number of
contexts was the amount of memory available.
There was no stack or heap to keep track of and operations involving
data in memory were faster than on other systems. It's a shame the CPU
never took off like Intel processors did.
Doesn't sound like this would be a win in today's world. The reason why
MIPS and similar architectures are easier to program for and frequently have
better compilers is that they have *lots* of registers. More registers is a
good thing- your program speeds up the less you have to hit memory. For
all of its faults, the best thing Itanium did was add a ton of registers.
Yeah, it slows down your context switches, but it speeds up your instruction
execute time. Unless you're running only 100-200 instructions between
switches, you're better off with lots of registers.
On top of that- the cpu speed:memory speed ratio is increasing. Requiring
all instructions to hit memory slows us down to the speed of the memory (in
this case, L1 cache). Cache is still slow to read. You'd end up gaining on
context switches, but losing on every instruction by being forced to
read/write memory instead of registers.
Interesting idea, but registers won for a reason.
Gabe
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