On 6/23/07, Darren New <[EMAIL PROTECTED]> wrote:
Bob La Quey wrote:
> IMHO it is a real pity that these architectures have not gotten
> an commerical traction.
Quoting...
"""
Using a realistic match of processor speed and affordable memory speed,
most processors can perform two internal stack operations in the time it
takes for a single memory access.
"""
I'm not sure what "realistic" means to the author, but...
The Harris 16 bit RTX 2000 was late 1980's 2 micron technology.
Clock speeds were ~ 10 Mhz. Chips could do an RTI in 2 clock cycles.
i.e. 200 ns.
At a 3GHz clock on a Pentium and a ~500MHz memory cycle time on desktop
computers, I suspect this architecture is better suited to embedded
devices. Generally, modern CPUs can blow the pants off a gigabyte-size
memory, speed-wise. RISC machines don't need a lot of registers or long
pipelines of the memory is clocked as fast as the CPU is.
If pigs had wings they could fly. You are looking here at
a 6 to 1 difference in external clock rate between the CPU
and the main memory.
When last I looked into this and it has been at
least a decade RISC cpus piped large numbers of
instructions through to effectively emulate what
a CISC was doing. In addition internal clock rates
were often higher than external ones. So the
mismatch was worse than just the external clock to
memory cycle would indicate.
The core problem for CISC and RISC emulating CISC is
=======================================
INT Call interrupt procedure
operands bytes 8088 186 286 386 486 Pentium
3 1 72 45 23+m 33 26
13 NP
imm8 2 71 47 23+m 37 30 16 NP
========================================
http://www.emboss.co.nz/pentopt/opcode_i.html
The interrupt response takes many clock cycles.
Andy can perhaps shed some light on the modern state
of affairs.
BobLQ
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