Bob La Quey wrote:
Clock speeds were ~ 10 Mhz. Chips could do an RTI in 2 clock cycles.
i.e. 200 ns.
If pigs had wings they could fly.
I'm not sure what that's supposed to imply... All I was pointing out is
that getting rid of registers and pipelines without losing efficiency is
much easier when your memory is about the same speed as your CPU, which
is not the case in desktop machines any more.
The core problem for CISC and RISC emulating CISC is
The interrupt response takes many clock cycles.
Except it's still faster than a 10MHz machine doing it in 2 clock
cycles, if I'm reading properly. :-)
Which is not to say the original author is wrong in what he wrote. He's
just addressing a different problem-space than the folks doing RISC (or,
for that matter, CISC) machines are addressing.
--
Darren New / San Diego, CA, USA (PST)
His kernel fu is strong.
He studied at the Shao Linux Temple.
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