The locic of kvm_apic_accept_pic_intr has a minor, practically hardly
relevant incorrectness: PIC interrupts are still delivered even if the
APIC of VPU0 (BSP) is disabled. This does not comply with the Virtual
Wire mode according to the Intel MP spec.
To avoid side effects, the BSP APIC is now enabled on reset.
Signed-off-by: Jan Kiszka <[EMAIL PROTECTED]>
---
arch/x86/kvm/lapic.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
Index: b/arch/x86/kvm/lapic.c
===================================================================
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -933,7 +933,8 @@ void kvm_lapic_reset(struct kvm_vcpu *vc
update_divide_count(apic);
atomic_set(&apic->timer.pending, 0);
if (vcpu->vcpu_id == 0)
- vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
+ vcpu->arch.apic_base |=
+ MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
apic_update_ppr(apic);
apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
@@ -1089,17 +1090,15 @@ int kvm_apic_has_interrupt(struct kvm_vc
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
{
+ struct kvm_lapic *apic = vcpu->arch.apic;
u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
- int r = 0;
- if (vcpu->vcpu_id == 0) {
- if (!apic_hw_enabled(vcpu->arch.apic))
- r = 1;
- if ((lvt0 & APIC_LVT_MASKED) == 0 &&
- GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
- r = 1;
- }
- return r;
+ /* Virtual Wire mode, but we only deliver to the BSP. */
+ if (vcpu->vcpu_id == 0 && apic_hw_enabled(apic)
+ && !(lvt0 & APIC_LVT_MASKED)
+ && GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
+ return 1;
+ return 0;
}
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
--
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