[ taking Sheng's comments into account ]
The logic of kvm_apic_accept_pic_intr has a minor, practically hardly
relevant incorrectness: PIC interrupts are still delivered even if the
APIC of VPU0 (BSP) is disabled. This does not comply with the Virtual
Wire mode according to the Intel MP spec.
Signed-off-by: Jan Kiszka <[EMAIL PROTECTED]>
---
arch/x86/kvm/lapic.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
Index: b/arch/x86/kvm/lapic.c
===================================================================
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1089,17 +1089,18 @@ int kvm_apic_has_interrupt(struct kvm_vc
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
{
- u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
- int r = 0;
+ struct kvm_lapic *apic = vcpu->arch.apic;
+ u32 lvt0 = apic_get_reg(apic, APIC_LVT0);
- if (vcpu->vcpu_id == 0) {
- if (!apic_hw_enabled(vcpu->arch.apic))
- r = 1;
- if ((lvt0 & APIC_LVT_MASKED) == 0 &&
- GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
- r = 1;
- }
- return r;
+ /*
+ * Virtual Wire mode, but we only deliver to the BSP.
+ * Note that apic_sw_enabled() is covered by testing for !LVT_MASKED.
+ */
+ if (vcpu->vcpu_id == 0 && apic_hw_enabled(apic)
+ && !(lvt0 & APIC_LVT_MASKED)
+ && GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
+ return 1;
+ return 0;
}
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
--
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