Hi, Multi level cache, translation lookaside buffers and a number of other items come to mind.
Paul -----Original Message----- From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Phil Payne Sent: Saturday, December 13, 2003 5:30 AM To: [EMAIL PROTECTED] Subject: Re: Technical Specs > And in each generation the pipelining abilities get better and better. Not always. 3033 ---> 3081? > For those who aren't up on the latest in processor design, > "pipelining" is a way for the CPU to actually execute more than one > instruction (or parts of a multi-cycle instruction) a single clock > cycle. Optimizing compilers can build instruction streams suited to > the capabilities of a particular processor, throwing the relationship > between instruction execution and cycle time (MHz) out the window. > You could end up with a 1GHz CPU executing instructions as though it > were, say, 1.3GHz. (I'm making those numbers up.) A simplification. The hardware does a whole RAFT of things that serve more to speed up the _environment_ than to speed up instruction execution. One major difference between the Intel environment and the IBM mainframe environment is that the former is principally designed for a single user and is therefore not strongly optimised for support of high-intensity task switching. The mainframe is; and so there's a whole load of hardware designed to preserve and restore the environment of an interrupted task as efficiently as possible. Run a single instruction loop and a modern Intel processor will clean the clock of even a z990. No contest. Start some serious task/address space switching and watch the ratios change - z990, at less than half the clock rate, will just leave Intel's best in the dust. -- Phil Payne http://www.isham-research.com +44 7785 302 803
