> Multi level cache, translation lookaside buffers and a number of other items come to mind.
Segment Table Origin Register Save Stacks. Each TLB entry is "tagged" with the STO it corresponds to. If an address space switch occurs, a new STO is loaded but the old one is saved in a stack and its TLB entries are tagged. If the old one is ever restored, the corresponding TLB entries are immediately returned to validity. Came in with the 3033, I believe. And other stuff. Loads of it. Cycle time isn't even a valid comparative metric between different generations of IBM processors, except that it shows what technology level they're using. And I'm not sure that is very interesting. Different CPU designers used different degrees of this stuff at different levels. In the 1980s, it seemed that IBM's designers were aiming at a sweet spot around 70% CPU - Amdahl's aimed at 95%. The relative performance of these systems changed with CPU load - the Amdahl machine got "faster" the more it was loaded. -- Phil Payne http://www.isham-research.com +44 7785 302 803
