On Wed, 2006-05-17 at 12:07 -0500, Tom Duerbusch wrote: > #4 Context switching. Seems like when you switch from one task to > another on some processors, all of cache is invalidated. Doesn't seem > to be so with the mainframe. I assume there is a point, where we > "thrash cache", but it seems like when we switch tasks on the mainframe, > your part of cache (instruction cache...stuff within the processor), > seems to stay in tack.
On x86 it is the translation-lookaside-buffers (TLBs) which get flushed each time the control register 1 is loaded. Switching between threads is fine because the use the same translation table. Switching between processes has a performance penalty. On mainframes the TLBs are not flushed for any context switch. The cache is a different story. Mainframes have the advantage of a shared level 2 cache compared to x86. If a process migrates from one processor to another, the cache lines of the process just have to be loaded from level 2 cache to level 1 cache again before they can be accessed. On x86 it goes over memory. -- blue skies, Martin. Martin Schwidefsky Linux for zSeries Development & Services IBM Deutschland Entwicklung GmbH "Reality continues to ruin my life." - Calvin. ---------------------------------------------------------------------- For LINUX-390 subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: INFO LINUX-390 or visit http://www.marist.edu/htbin/wlvindex?LINUX-390
