I've always wanted to ask this question and you seem like someone who would
know. First and foremost I am not a computer engineer!
Here's the situation.
When the PC first came out I taught myself some basic assembler for the x86
chip. One thing that I remember to move 255 bytes from one location to another
I had to set up a count register, source register, and target register. The
move instruction was executed in a loop that decemented/incremented (I don't
remember which) the counter. While I'm sure there is a lot of stuff that
happens at the microcode level of the mainframe, we use one assembler
instruction to move 255 bytes. From what I remember of x86 assembler it took
more instructions to do things than it did on the mainframe. If the the x86
chip were faster than the mainframe's chip, would some of that speed be lost
because it takes more instructions to do the same task?
Please be kind in responding. Like I said this stuff is really over my head!
>>> [EMAIL PROTECTED] 5/18/2006 9:51:12 AM >>>
Yes tagging works, but you will find that the system z holds a lot more
translations in a two tiered TLB and has tagging as well. Thus the System
z does not have to retranslate as often.
Joe Temple
Distinguished Engineer
Sr. Certified IT Specialist
[EMAIL PROTECTED]
845-435-6301 295/6301 cell 914-706-5211
Home office 845-338-1448 Home 845-338-8794
Alan Cox
<[EMAIL PROTECTED]
u.org.uk> To
Sent by: Linux on [email protected]
390 Port cc
<[EMAIL PROTECTED]
IST.EDU> Subject
Re: Fw: [LINUX-390] Who's been
reading our list...
05/18/2006 07:23
AM
Please respond to
Linux on 390 Port
<[EMAIL PROTECTED]
IST.EDU>
On Iau, 2006-05-18 at 10:03 +0200, Martin Schwidefsky wrote:
> On x86 it is the translation-lookaside-buffers (TLBs) which get flushed
> each time the control register 1 is loaded. Switching between threads is
[%cr3 not 1 but thats by the way]
> fine because the use the same translation table. Switching between
> processes has a performance penalty. On mainframes the TLBs are not
> flushed for any context switch.
Not on a current AMD x86 processor. The opteron and AMD64 processor line
uses tags on the tlb entries so that it can avoid this without the
underlying OS being changed.
> The cache is a different story. Mainframes have the advantage of a
> shared level 2 cache compared to x86. If a process migrates from one
> processor to another, the cache lines of the process just have to be
> loaded from level 2 cache to level 1 cache again before they can be
> accessed. On x86 it goes over memory.
Long ago yes but even with private L2 caches (which have advantages too)
you can send lines from cache to cache directly if your bus protocol is
sane.
Alan
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