On Iau, 2006-05-18 at 10:03 +0200, Martin Schwidefsky wrote: > On x86 it is the translation-lookaside-buffers (TLBs) which get flushed > each time the control register 1 is loaded. Switching between threads is
[%cr3 not 1 but thats by the way] > fine because the use the same translation table. Switching between > processes has a performance penalty. On mainframes the TLBs are not > flushed for any context switch. Not on a current AMD x86 processor. The opteron and AMD64 processor line uses tags on the tlb entries so that it can avoid this without the underlying OS being changed. > The cache is a different story. Mainframes have the advantage of a > shared level 2 cache compared to x86. If a process migrates from one > processor to another, the cache lines of the process just have to be > loaded from level 2 cache to level 1 cache again before they can be > accessed. On x86 it goes over memory. Long ago yes but even with private L2 caches (which have advantages too) you can send lines from cache to cache directly if your bus protocol is sane. Alan ---------------------------------------------------------------------- For LINUX-390 subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: INFO LINUX-390 or visit http://www.marist.edu/htbin/wlvindex?LINUX-390
