Adam 'WeirdArms' Wiggins writes:
> On Tue, 14 Sep 1999, Philip Blundell wrote:
> > > Would the following instruction use the user_sp or the svc_sp as
> > >the base register if run in svc mode:
> > >
> > > stmdb sp, {sp, lr}^ @ Stack usr_sp, usr_lr
> >
> > The architecture may leave it undefined. Back in days of yore (ARM2 and so
> > on) I am fairly sure it took the base from the current register bank, ie SVC.
> > If you asked for writeback then the base would be read from the SVC bank but
> > written back to the USR one which is probably not what you'd want.
>
> Don't care about write back (not using it in this case). I'm
> interested in gerneral ARM3/4. In particular StrongARM but I have a
> PS7110 (Psion 5) unit too. What do these chips do?
I would recommend against this instruction. There has already been one
bug in the StrongARM related to user-mode STMs from SVC. I think that
the general advice given at that time was not to use any banked register
with a user-mode stm.
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