> > Don't care about write back (not using it in this case). I'm
> > interested in gerneral ARM3/4. In particular StrongARM but I have a
> > PS7110 (Psion 5) unit too. What do these chips do?
>
> I would recommend against this instruction. There has already been one
> bug in the StrongARM related to user-mode STMs from SVC. I think that
> the general advice given at that time was not to use any banked register
> with a user-mode stm.
If this is the one concerning page faults during a stm then its
not relavent (kernel stacks in this case never cross page bounds). If its
something else please forward the details to me.
Many thanks, Adam
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