> Would the following instruction use the user_sp or the svc_sp as
>the base register if run in svc mode:
>
> stmdb sp, {sp, lr}^ @ Stack usr_sp, usr_lr
The architecture may leave it undefined. Back in days of yore (ARM2 and so
on) I am fairly sure it took the base from the current register bank, ie SVC.
If you asked for writeback then the base would be read from the SVC bank but
written back to the USR one which is probably not what you'd want.
p.
unsubscribe: body of `unsubscribe linux-arm' to [EMAIL PROTECTED]
