Hi Charles,
> Channel capacity is defined as the maximum rate for reliable
> communication through a channel. This is a function of many things,
> channel bandwidth, noise spectrum, SNR and a whole bunch of other
> things.
Well, more exactly as Shannon proved around 1948,
C = B*ld(1+SNR) ld : logarithm dualis (base 2)
Where C is channel capacity in bps, B is Bandwidth in Hz, SNR is the
average signal to noise ratio (linear, not logarithmic). For example,
a standart-25KHz-channel with a SNR of 20dB has a capacity of around
166,4 Kbps.
Note however, that the above SNR value is baseband snr. The FM
demodulation process changes the noise desity spectrum. High frequency
regions contain more noise energy than low frequencies. That�s why
most FM tranceivers for voice transmission do pre/deemphasis.
> How to achieve channel capacity in the general case is a
> challenging problem. It has been solved in some cases.
Right, the above numbers only have a theoretical meaning. However,
using convolutional codes with iterative decoders ("turbo codes") for
example, with very high constraint lengths (=>full duplex only), allow
to aproximate the theoretical limit by about 0.4 dB.
>[...]
> Demodulations can be computationally intensive. 56k modems usually have
> an ASIC or a dedicated processor to deal with the load. My question
> is: Where are the computational bottlenecks and can anything be done
> about them?
Due my experiments I found out that the most processing time is consumed
by the FIR filter in the demodulator input. This FIR filter must be used
to
increase the oversampling ratio (sample rate conversion) to ensure a
usuable
PLL clock recovery phase shift resolution. However, if done right every
old
i486 can cope with soundcard input sampling rates (48 KHz that is).
The only difference between usual host CPUs and DSPs is the execution
time of a multiply-and-sum-up operation. DSPs are tweaked to execute
such
an instruction (or series) in only one clock cycle. The multiply-and-sum
operation is used when implementing filter operations in time domain
(convolution). However, as Phil proves (http://people.qualcomm.com/karn)
pentium (TM) class processors reach a performance of 3 cycles if used
with hand-optimized assembler code (integer).
-- Jens
