Add Juno r2 cpu capacity-dmips-mhz information.

Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Liviu Dudau <liviu.du...@arm.com>
Cc: Sudeep Holla <sudeep.ho...@arm.com>
Cc: Arnd Bergmann <a...@arndb.de>
Cc: Jon Medhurst <t...@linaro.org>
Cc: Olof Johansson <o...@lixom.net>
Cc: Robin Murphy <robin.mur...@arm.com>
Cc: devicet...@vger.kernel.org
Signed-off-by: Juri Lelli <juri.le...@arm.com>
Acked-by: Sudeep Holla <sudeep.ho...@arm.com>
---

Changes from v4:
  - new patch since Juno r2 dt has been merged

Changes from v6:
  - s/bindings// in changelog
---
 arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts 
b/arch/arm64/boot/dts/arm/juno-r2.dts
index 007be826efce..614fc9227943 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -90,6 +90,7 @@
                        next-level-cache = <&A72_L2>;
                        clocks = <&scpi_dvfs 0>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <1024>;
                };
 
                A72_1: cpu@1 {
@@ -100,6 +101,7 @@
                        next-level-cache = <&A72_L2>;
                        clocks = <&scpi_dvfs 0>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <1024>;
                };
 
                A53_0: cpu@100 {
@@ -110,6 +112,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <485>;
                };
 
                A53_1: cpu@101 {
@@ -120,6 +123,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <485>;
                };
 
                A53_2: cpu@102 {
@@ -130,6 +134,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <485>;
                };
 
                A53_3: cpu@103 {
@@ -140,6 +145,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <485>;
                };
 
                A72_L2: l2-cache0 {
-- 
2.10.0

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