Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.

Cc: Rajendra Nayak <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Paul Walmsley <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Kumar Gala <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index fe5db55..b48f18b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
                ti,bit-shift = <8>;
        };
 
+       optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&sys_32k_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <8>;
+       };
+
        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
                compatible = "ti,divider-clock";
                clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@
                ti,bit-shift = <9>;
        };
 
+       optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&apll_pcie_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <9>;
+       };
+
        optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
                compatible = "ti,gate-clock";
                clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@
                ti,bit-shift = <10>;
        };
 
+       optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&optfclk_pciephy_div>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <10>;
+       };
+
        apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
-- 
1.7.9.5

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