Seems that 0x248 show up in https://download.01.org/perfmon/HSW/ but not in manual. If 0x248 does not exist, then the code should be correct.
On Thu, Nov 12, 2015 at 1:00 PM, Vince Weaver <vincent.wea...@maine.edu> wrote: > > ccing Andi Kleen as he's the one who introduced the Haswell constraint > code in 3a632cb229bfb18b6d09822cc842451ea46c013e so maybe he knows why > it is contraining all L1D_PEND_MISS.* events rather than just > L1D_PEND_MISS.PENDING on IVB and BDW. > > On Thu, 12 Nov 2015, Vince Weaver wrote: > >> On Thu, 12 Nov 2015, Michael Petlan wrote: >> >> > But I can't find any reference about the r1000248 event >> > in the Intel Manual. Vince, am I missing something? >> > >> > Anyway, shouldn't it behave the same on IVB and HSW? >> >> I am going off the code in >> arch/x86/kernel/cpu/perf_event_intel.c >> (current git tree) >> >> SNB and HSW have as a constraint >> INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */ >> >> IVB has as a constraint >> INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ >> >> Notice the difference. Not sure if this is a bug in the kernel or what, >> but that's what's there and I think it's what's causing the issue. >> >> Vince -- To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
