Is this ok?
>From 47d52ccfae56a8eb702fee6ccf327780265df2cf Mon Sep 17 00:00:00 2001
From: Yuanfang Chen <ch...@udel.edu>
Date: Mon, 16 Nov 2015 21:53:53 -0500
Subject: [PATCH 1/1] perf/x86/intel: make L1D_PEND_MISS.FB_FULL not
constrained on haswell
Signed-off-by: Yuanfang Chen <ch...@udel.edu>
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index f63360b..e2a4300 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -232,7 +232,7 @@ static struct event_constraint
intel_hsw_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
- INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
+ INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
/* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
--
1.9.1
On Mon, Nov 16, 2015 at 7:39 PM, Andi Kleen <a...@linux.intel.com> wrote:
> On Thu, Nov 12, 2015 at 01:00:09PM -0500, Vince Weaver wrote:
>>
>> ccing Andi Kleen as he's the one who introduced the Haswell constraint
>> code in 3a632cb229bfb18b6d09822cc842451ea46c013e so maybe he knows why
>> it is contraining all L1D_PEND_MISS.* events rather than just
>> L1D_PEND_MISS.PENDING on IVB and BDW.
>
> Yes it looks like Haswell could use the more limited constraint as Broadwell
> or IvyBridge. I don't remember why it ended up this way.
> Please submit a patch.
>
> -Andi
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